1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, a semiconductor memory device having a redundancy circuit.
2. Description of the Related Invention
Modern graphic systems with enhanced resolution and three-dimensional capability often include RAMBUS.TM. DRAM (Dynamic Random Access Memory) or MMLs (Merged Memory Logic) to satisfy the memory requirements for effective graphic operation. RAMBUS DRAMs and MMLs have more data I/O (input and output) lines than column select lines to increase data I/O bits. These semiconductor memory devices have word lines and column select lines extending in the same direction and data I/O lines and bit lines extending perpendicular to the word lines.
The above-described semiconductor memory devices generally include redundant data I/O lines connected to redundancy memory cells for replacement of defective memory cells and associated data I/O lines. Using these redundancy circuits, a redundancy method can replace a defective bank, block, or column address group with a redundant bank, block, or column address group.
FIG.1 is a block diagram of a semiconductor memory device using a known bank redundancy method. The semiconductor memory device includes two memory cell array banks BANK0 and BANK1, and each of the two memory cell array banks BANK0 and BANK1 contains four memory cell arrays BLA, BLB, BLC, and BLD. Each of the four memory cell arrays includes a normal block NB and a redundant block RB. In a bank redundancy method, if a partial block 1 of array BLA of bank BANK0 and a partial block 2 of array BLA of bank BANK1 are defective, partial blocks 1 and 2 and all partial blocks in corresponding locations of arrays BLB, BLC, BLD, are replaced with redundant blocks RB. Redundant blocks RB thus replace the partial blocks hatched on the left portions of arrays BLA, BLB, BLC, and BLD. Accordingly, a data I/O line IO1 associated with the replaced blocks is replaced with a redundant data I/O line RIO.
If partial block 2 of array BLA and a partial block 3 of array BLB of bank BANK1 are defective, one of the partial blocks 2 and 3 can be replaced with the redundant block RB, but the other partial block cannot be replaced with the redundant block RB. Accordingly, the bank redundancy method cannot repair this pattern of memory cell defects. That is, the bank redundancy method cannon repair the defective memory when two or more data il lines are associated with defective memory cells. A block redundancy method can repair the partial blocks 2 and 3. FIG. 2 is a block diagram of a semiconductor memory device using a known block redundancy method. The device has the same structure as the device of FIG. 1. Referring to FIG. 2, when partial blocks 1' and 2' of arrays BLA and BLB of BANK0 are defective, the block redundancy method replaces defective partial blocks 1' and 2' with redundant blocks RB of blocks BLA and BLB of bank BANK0. The method further replaces partial blocks (hatched in the same fashion as partial blocks 1' and 2')of bank BANK1, which are equivalently located to partial blocks 1' and 2' of bank BANK0, with redundant blocks RB of the memory cell arrays BLA and BLB of bank BANK1. In this method, redundant date I/O line RIO replaces data I/O line IO1 or IO4 depending on the array accessed.
When partial blocks 1' and 3' of array BLA of bank BANKO are defective, only one of partial blocks 1' of the memory cell array block BLA can be replaced with the redundant partial block RB of array BLA. That is, the block redundancy method cannot repair multiple defective partial blocks in the same memory cell array.
FIG. 3 is a block diagram of a semiconductor memory device using a known column address group redundancy method. The device has the same structure as the device of FIG except that each partial block (including redundant partial block RB) includes four portions distinguished by column address group.
When defective portions 1" and 2" of array BLA of bank BANK0 are in different column address groups, the column address group redundancy method replaces defective portions 1" and 2" of bank BANK0 (and all portions of banks BANK0 and BANK1 in the same columns as portions 1" and 2") with the portions of redundant partial blocks RB that are respectively associated with the same column address group as portions 1" and 2". In FIG. 3, the crosshatched portions replace the hatched portions in respective arrays BLA, BLB, BLC, and BLD. Here, redundant data I/O line RIO replaces data I/O lines I01 and I04 when accessing columns corresponding to portions 1" and 2".
However, when portions 1" and 3", which are associated to the same column address group, are defective, the column address group redundancy method can replace only one of portions 1" and 3" with the corresponding portion of redundant partial block RB. That is, the column address group redundancy method cannot repair this kind of defect pattern.
Semiconductor memory devices usually select one of the three redundancy methods described above and thus cannot repair all kinds of defective memory cell patterns.